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CS5321/22 24-bit, Variable-bandwidth A/D Converter Chipset
Features
CMOS A/D Converter Chipset Dynamic Range
- 130 dB @ 25 Hz Bandwidth - 121 dB @ 411 Hz Bandwidth
Description
The CS5321/CS5322 chipset functions as a unique A/D converter intended for very high-resolution measurement of signals below 1600 Hz. It is specifically designed for applications that require both a high dynamic range and a low total harmonic distortion. The chipset performs sampling, A/D conversion, and anti-alias filtering. The CS5321 uses Delta-Sigma modulation to produce highly accurate conversions. The modulator oversamples, virtually eliminating the need for external analog anti-alias filters. The CS5322 linear-phase FIR digital filter decimates the output to any one of seven selectable update periods: 16, 8, 4, 2, 1, 0.5, and 0.25 milliseconds. Data is output from the digital filter in a 24-bit serial format.
ORDERING INFORMATION
Delta-sigma Architecture
- Fourth-order Modulator - Variable Oversampling: 64X to 4096X - Internal Track-and-hold Amplifier
CS5321 Signal-to-distortion: 115 dB Clock-jitter-tolerant Architecture Input Voltage Range: +4.5 V Flexible Filter Chip
- Hardware- or Software-selectable Options - Seven Selectable Filter Corners (-3 dB) Frequencies: 25, 51, 102, 205, 411, 824 and 1650 Hz
Low Power Dissipation: <100 mW
See page 36.
CS5321
Vdd1 Vss1 Vdd2 Vss2 LPWR OFST MSYNC AINR AIN+ AINVREF+ VREFAGND DGND HBR Analog Modulator MDATA MFLG MCLK MDATA VD+ DGND CSEL H/S TDATA RESET VD+ SYNC
CS5322
CLKIN CS R/W RSEL SCLK SID SOD Digital Filter ERROR DRDY ORCAL DECA DECB DECC PWDN USEOR DGND
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2006 (All Rights Reserved)
NOV `06 DS454F3
CS5321/22
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ............................................... 4 CS5321 ANALOG CHARACTERISTICS .................................................... 4 CS5321 SWITCHING CHARACTERISTICS .............................................. 6 CS5321 DIGITAL CHARACTERISTICS ..................................................... 7 CS5321 RECOMMENDED OPERATION CONDITIONS ........................... 7 CS5321 ABSOLUTE MAXIMUM RATINGS ............................................... 7 CS5322 FILTER CHARACTERISTICS ...................................................... 8 CS5322 POWER SUPPLY ....................................................................... 10 CS5322 SWITCHING CHARACTERISTICS ............................................ 10 CS5322 DIGITAL CHARACTERISTICS ................................................... 15 CS5322 RECOMMENDED OPERATION CONDITIONS ......................... 15 CS5322 ABSOLUTE MAXIMUM RATINGS ............................................. 15 2. GENERAL DESCRIPTION ............................................................................ 16 2.1. Analog Input ...................................................................................... 18 2.2. The OFST Pin.................................................................................... 18 2.3. Input Range and Overrange Conditions ............................................ 19 2.4. Voltage Reference ............................................................................. 20 2.5. Clock Source ..................................................................................... 20 2.6. Low Power Mode ............................................................................... 21 2.7. Digital Interface and Data Format...................................................... 21 2.8. Performance ...................................................................................... 22 2.9. Power Supply Considerations............................................................ 23 2.10. Power Supply Rejection Ratio ......................................................... 23 2.11. RESET Operation ............................................................................ 23 2.12. Power-down Operation .................................................................... 23 2.13. SYNC Operation .............................................................................. 24 2.14. Serial Read Operation ..................................................................... 24 2.15. Serial Write Operation ..................................................................... 24 2.16. Offset Calibration Operation ............................................................ 25 2.17. Status Bits ....................................................................................... 26 2.18. Board Layout Considerations .......................................................... 28 3. CS5321 PIN DESCRIPTIONS ....................................................................... 29 Power Supplies ......................................................................................... 29 Analog Inputs ............................................................................................ 29 Digital Inputs ............................................................................................. 30 Digital Outputs .......................................................................................... 30 4. CS5322 PIN DESCRIPTIONS ....................................................................... 31 Power Supplies ......................................................................................... 31 Digital Outputs .......................................................................................... 31 Digital Inputs ............................................................................................. 32 5. PARAMETER DEFINITIONS......................................................................... 34 6. PACKAGE DIMENSIONS.............................................................................. 35 7. ORDERING INFORMATION ......................................................................... 36 8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ... 36 9. REVISION HISTORY .................................................................................... 36
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LIST OF FIGURES
Figure 1. Rise and Fall Times ..................................................................................... 6 Figure 2. CS5321 Interface Timing, HBR=1 ............................................................... 6 Figure 3. CS5322 Filter Response ............................................................................. 8 Figure 4. CS5322 Digital Filter Passband Ripple, f0 = 62.5 Hz .................................. 8 Figure 5. CS5322 Digital Filter Passband Ripple, f0 = 125 Hz ................................... 8 Figure 6. CS5322 Digital Filter Passband Ripple, f0 = 250 Hz ................................... 8 Figure 7. CS5322 Digital Filter Passband Ripple, f0 = 500 Hz ................................... 9 Figure 8. CS5322 Digital Filter Passband Ripple, f0 = 1000 Hz ................................. 9 Figure 9. CS5322 Digital Filter Passband Ripple, f0 = 2000 Hz ................................. 9 Figure 10. CS5322 Digital Filter Passband Ripple, f0 = 4000 Hz ............................... 9 Figure 11. CS5322 Impulse Response, f0 = 62.5 Hz .................................................. 9 Figure 12. CS5322 Impulse Response, f0 = 1000 Hz ................................................. 9 Figure 13. CS5322 Serial Port Timing ...................................................................... 11 Figure 14. TDATA Setup/Hold Timing ...................................................................... 12 Figure 15. DRDY Timing .......................................................................................... 13 Figure 16. RESET Timing ......................................................................................... 13 Figure 17. CS5321/CS5322 Interface Timing ........................................................... 14 Figure 18. CS5321 Block Diagram ........................................................................... 16 Figure 19. CS5322 Block Diagram ........................................................................... 17 Figure 20. System Connection Diagram ................................................................... 19 Figure 21. 4.5 Voltage Reference with two filter options .......................................... 20 Figure 22. 1024 Point FFT Plot with -20 dB Input, 100 Hz Input, ten averages 22 Figure 23. 1024 Point FFT Plot with Full Scale Input, 100 Hz Input, HBR = 1, ten averages ............................................. 22 Figure 24. 1024 Point FFT Plot with Full Scale Input, 100 Hz Input, HBR = 0, ten averages ............................................. 22
LIST OF TABLES
Table 1. Table 2. Table 3. Table 4. Output Coding for the CS5321 and CS5322 Combination ....................... 21 Configuration Data Bits ............................................................................ 25 Status Data (from the SOD Pin) ............................................................... 26 Bandwidth Selection: Truth Table ............................................................ 27
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1. CHARACTERISTICS AND SPECIFICATIONS
CS5321 ANALOG CHARACTERISTICS (TA = (See Note 1); Vss1, Vss2 = -5 V; Vdd1, Vdd2 = +5 V;
VD+ = 5 V; AGND = DGND = 0 V; HBR = Vdd LPWR = 0, MCLK = 1.024 MHz; Device connected as shown in Figure 20, CS5322 used for filtering; Logic 1 = VD+, Logic 0 = 0V; unless otherwise specified.) CS5321 Parameter* Dynamic Performance Dynamic Range HBR = 1 OFST = 1 (Note 2) fO = 4000 Hz fO = 2000 Hz fO = 1000 Hz fO = 500 Hz fO = 250 Hz fO = 125 Hz fO = 62.5 Hz fO = 4000 Hz fO = 2000 Hz fO = 1000 Hz fO = 500 Hz fO = 250 Hz fO = 125 Hz fO = 62.5 Hz (Note 3) HBR = 1 HBR = 0 (Note 4) (Note 5) (Note 5,6) (Note 5) (Note 7) (Note 8) (Note 5,6) TCZSE SDR 108 110 IMD FSE TCFS VZSE 115 120 110 1 5 10 100 100 60 dB dB dB %
ppm/C
Symbol DR
Min
Typ
Max
Unit
116 -
103 118 121 124 127 129 130 99 115 118 121 124 126 127
-
dB dB dB dB dB dB dB dB dB dB dB dB dB dB
HBR = 0 OFST = 1
Signal-to-Distortion
Intermodulation Distortion DC Accuracy Full Scale Error Full Scale Drift Offset Offset after Calibration Offset Calibration Range Offset Drift
mV V %F.S. V/C
Notes: 1. CS5321-BL is guaranteed from -55o to +85o C, CS5322-BL is guaranteed from -40o to +85o C. 2. fO = CS5322 output word rate. Refer to "CS5322 FILTER CHARACTERISTICS" on page 8 for details on the FIR Filter. 3. Characterized with full scale input signal of 50 Hz; fo = 500 Hz. 4. Characterized with input signals of 30 Hz and 50 Hz, each 6 dB down from full scale with fo = 1000 Hz. 5. Specification is for the parameter over the specified temperature range and is for the CS5321 device only (VREF = +4.5 V). It does not include the effects of external components; OFST = 0. 6. Drift specifications are guaranteed by design and/or characterization. 7. The offset after calibration specification applies to the effective offset voltage for a 4.5 volt input to the CS5321 modulator, but is relative to the output digital codes from the CS5322 after ORCAL and USEOR have been made active. 8. The CS5322 offset calibration is performed digitally and includes full scale (4.5 volts into CS5321). Calibration of offsets greater than 5% of full scale will begin to subtract from the dynamic range.
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CS5321 ANALOG CHARACTERISTICS (Continued)
CS5321 Parameter* Input Characteristics Input Signal Frequencies Input Voltage Range Input Overrange Voltage Power Supplies DC Power Supply Currents (Note 11) LPWR = 0 Positive Supplies Negative Supplies LPWR = 1 Positive Supplies Negative Supplies PDN PDL PD (dc to 128 kHz) (Note 14) PSR 5.5 5.5 3.0 3.0 55 30 2 60 7.5 7.5 4.5 4.5 75 45 mA mA mA mA mW mW mW dB (Note 9) (Note 10) (Note 10) BW VIN IOVR DC -4.5 1600 +4.5 5 Hz V %F.S. Symbol Min Typ Max Unit
Power Consumption
(Note 11) Normal Operating Mode (Note12) Lower Power Mode (Note 13)
-
Power Down Power Supply Rejection
Notes: 9. The upper bandwidth limit is determined by the CS5322 digital filter. 10. This input voltage range is for the configuration shown in Figure 20, the System Connection Diagram, and applies to signal from dc to f3 Hz. Refer to CS5322 Filter Characteristics for the values of f3. 11. All outputs unloaded. All logic inputs forced to Vdd or GND respectively. 12. LPWR = 0. 13. The CS5321 power dissipation can be reduced under the following conditions: a) LPWR=1; MCLK=512 kHz, HBR=1 b) LWPR=1; MCLK=1.024 MHz, HBR=0 14. Characterized with a 100 mVp-p sine wave applied separately to each supply. * Refer to Parameter Definitions (immediately following pin descriptions at the end of this data sheet). Specifications are subject to change without notice.
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CS5321 SWITCHING CHARACTERISTICS (TA = (See Note 1); Vdd1, Vdd2 = 5 V 5%; Vss1,
Vss2 = -5 V 5%; Inputs: Logic 0 = 0 V Logic 1 = V+; CL = 50 pF (Note 15)) Parameter MCLK Frequency MCLK Duty Cycle MCLK Jitter (In-band) Rise Times: Fall Times: Any Digital Input Any Digital Output Any Digital Input Any Digital Output (Note 17) (Note 17) trisein triseout tfallin tfallout tmss tmsh tmfh tmdv (Note 16) Symbol fc Min 0.250 40 20 20 Typ 1.024 50 50 140 170 Max 1.2 60 300 100 200 100 200 255 300 Units MHz % ps ns ns ns ns ns ns ns ns
MSYNC Setup Time to MCLK rising MSYNC Hold Time after MCLK rising MCLK rising to Valid MFLG MCLK rising to Valid MDATA
Notes: 15. Guaranteed by design, characterization, or test. 16. If MCLK is removed, the modulator will enter the power down mode. 17. Excludes MCLK input. MCLK should be driven with a signal having rise and fall times of 25 ns or faster.
t rise in
t fa llin 4.0 V 1.0 V
t rise out
t fallo ut 4 .6 V 0 .4 V
Figure 1. Rise and Fall Times
M C LK t mss
t m sh
MSYNC t m dv M D A TA V A L ID D A TA t m dv V A L ID D A T A
t m fh M F LG
Figure 2. CS5321 Interface Timing, HBR=1
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CS5321 DIGITAL CHARACTERISTICS (TA = (See Note 1); Vdd1 = Vdd2
0 V; measurements performed under static conditions) Parameter High-Level Input Drive Voltage Low-Level Input Drive Voltage High-Level Output Voltage IOUT = -40 A Low-Level Output Voltage IOUT = +40 A Input Leakage Current Digital Input Capacitance Digital Output Capacitance (Note 18) (Note 18) (Note 19) (Note 19) Symbol VIH VIL VOH VOL ILKG CIN COUT Min (Vdd)-0.6 (Vdd)-0.3 Typ 9 9 Max 1.0 0.3 10 Units V V V V A pF pF = 5.0 V 5%; GND =
Notes: 18. Device is intended to be driven with CMOS logic levels. 19. Device is intended to be interfaced to CMOS logic. Resistive loads are not recommended on these pins.
CS5321 RECOMMENDED OPERATION CONDITIONS (Voltages with respect to GND =
0 V, See Note 20) Parameter DC Supply: Ambient Operating Temperature Symbol Positive Vdd1,Vdd2 Negative Vss1,Vss2 -BL TA Min 4.75 -4.75 -55 Typ 5.0 -5.0 Max 5.25 -5.25 +85 Units V V C
Notes: 20. The maximum voltage differential between the Positive Supply of the CS5321 and the Positive Digital Supply of the CS5322 must be less than 0.25 V.
CS5321 ABSOLUTE MAXIMUM RATINGS * (Voltages with respect to GND = 0 V)
Parameter DC Supply: Input Current, Any Pin Except Supplies Output Current Total Power (all supplies and outputs) Digital Input Voltage Storage Temperature Positive Negative (Note 21) Symbol Vdd1,Vdd2 Vss1,Vss2 Iin Iout Pt VIND Tstg Min -0.3 +0.3 -0.3 -65 Max 6.0 -6.0 10 25 1 (Vdd)+0.3 150 Units V V mA mA W V C
Notes: 21. Transient currents of up to 100 mA will not cause SCR latch up. *WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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CS5322 FILTER CHARACTERISTICS (TA = (See Note 1); VD+ = 5.0 V; GND = 0 V;
CLKIN = 1.024 MHz; transfer function shown in Figure 3; unless otherwise specified.) Output Word Rate f0 (Hz) 4000 2000 1000 500 250 125 62.5 Passband f1 (Hz) 1500 750 375 187.5 93.8 46.9 23.4 Passband Flatness RPB (dB) 0.2 0.04 0.08 0.1 0.1 0.1 0.1 -3dB Freq. f2 Stopband f3 (Hz) (Hz) (Note 22) 1652.5 824.3 411.9 205.9 102.9 51.5 25.7 2000 1000 500 250 125 62.5 31.25 Group Delay (ms) 7.25 14.5 29 58 116 232 464
Notes: 22. GSB = -130 dB for all Output Word Rates.
dB 0 -3
G SB
-13 0
f1
f2
f3
f
Figure 3. CS5322 Filter Response Figure 4. CS5322 Digital Filter Passband Ripple
f0 = 62.5 Hz
Figure 5. CS5322 Digital Filter Passband Ripple f0 = 125 Hz
Figure 6. CS5322 Digital Filter Passband Ripple f0 = 250 Hz
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Figure 7. CS5322 Digital Filter Passband Ripple f0 = 500 Hz
Figure 8. CS5322 Digital Filter Passband Ripple f0 = 1000 Hz
Figure 9. CS5322 Digital Filter Passband Ripple f0 = 2000 Hz
-5 ,2 06 ,2 5 0
-5 ,2 12 ,5 0 0
Figure 10. CS5322 Digital Filter Passband Ripple f0 = 4000 Hz
-5 ,2 06,25 0 -5 ,2 0 8,3 28 -5 ,2 12,50 0
-5 ,2 18 ,7 5 0 D ig ital O utpu t C o d e -5 ,2 25 ,0 0 0 -5 ,2 31 ,2 5 0 -5 ,2 4 0 ,7 2 3 -5 ,2 37 ,5 0 0
-5 ,2 43 ,7 5 0
D igital O u tput C o de
-5 ,2 18,75 0
-5 ,2 25,00 0
-5 ,2 31,25 0
-5 ,2 37,50 0
-5 ,2 43,75 0
-5 ,2 50 ,0 0 0
1 8 15 22 29 36 43 50 57
-5 ,2 50,00 0 1 8 15 22 29 36 43 50 57
T im e (# o f O u tp u t W o rd s)
T im e (# o f O utp u t W o rd s)
Figure 11. CS5322 Impulse Response, f0 = 62.5 Hz
Figure 12. CS5322 Impulse Response, f0 = 1000 Hz
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CS5322 POWER SUPPLY (TA = (See Note 1); VD+ = 5 V; CLKIN = 1.024 MHz)
CS5322-BL Parameter Power Supply Current: Power Dissipation: ID+ (Note 11) (Note 11) PWDN Low PWDN High Min Typ 2.2 11 0.6 Max 4 20 2.5 Unit mA mW mW
CS5322 SWITCHING CHARACTERISTICS (TA = (See Note 1); VD+ = 5 V 5%; DGND = 0 V;
Inputs: Logic 0 = 0 V Logic 1 = VD+; CL = 50 pF (Note 23) Parameter CLKIN Frequency CLKIN Duty Cycle Rise Times: Fall Times: Serial Port Read Timing DRDY to Data Valid RSEL Setup Time before Data Valid Read Setup before CS Active Read Active to Data Valid SCLK rising to New SOD bit SCLK Pulse Width High SCLK Pulse Width Low SCLK Period SCLK falling to DRDY falling CS High to Output Hi-Z Read Hold Time after CS Inactive Read Select Setup to SCLK falling Serial Port Write Timing Write Setup Before CS Active SCLK Pulse Width Low SCLK Pulse Width High SCLK Period Write Setup Time to First SCLK falling Data Setup Time to First SCLK falling Write Select Hold Time after SCLK falling Write Hold Time after CS Inactive Data Hold Time after SCLK falling 23. Guaranteed by design, characterization and/or test. 10 DS454F3 twsc twpl twph twsp twws twds twwh twhc twdh 20 30 30 100 20 20 20 20 20 ns ns ns ns ns ns ns ns ns tddv trss trsc trdv trdd trph trpl trsp trst trch trhc trds 50 20 30 30 100 20 20 25 50 50 50 20 ns ns ns ns ns ns ns ns ns ns ns ns Any Digital Input Any Digital Output Any Digital Input Any Digital Output trise tfall Symbol fc Min 0.512 40 Typ 1.024 50 50 Max 1.2 60 100 100 100 100 Units MHz % ns ns ns ns
CS5321/22
t rss RSEL
DRDY
t ddv t rst
R /W t rsc CS t rdv SOD H i-Z MSB M S B -1 t rdd S C LK t rph t rds
Serial Port Read Timing (R/W = 1, CS = 0, RSEL = 1 DRDY Does not toggle if reading status, RSEL = 0)
t rhc
t rch LS B + 1 LSB H i-Z
t rpl
t rsp
CS t w sc R /W t wws SCLK t wds S ID MSB t w sp t wdh M S B -1
Serial Port Write Timing
Figure 13. CS5322 Serial Port Timing
t whc
t wph t wwh
t wpl LS B+1 LSB
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CS5322 SWITCHING CHARACTERISTICS (continued)
Parameter Test Data (TDATA) Timing SYNC Setup Time to CLKIN rising SYNC Hold Time after CLKIN rising TDATA Setup Time to CLKIN rising after SYNC TDATA Hold Time after CLKIN rising ORCAL Setup Time to CLKIN rising ORCAL Hold Time after CLKIN rising DRDY Timing CLKIN rising to DRDY falling CLKIN falling to DRDY rising CLKIN rising to ERROR change RESET Timing RESET Setup Time to CLKIN rising RESET Hold Time after CLKIN rising SYNC Setup Time to CLKIN rising SYNC Hold Time after CLKIN rising trs trh tss tsh 20 20 20 20 ns ns ns ns tdf tdr tec 140 150 140 ns ns ns tss tsh ttds ttdh tos toh 20 20 20 20 20 150 ns ns ns ns ns ns Symbol Min Typ Max Units
C L K IN t sh
t ss SYNC
t oh t os ORCAL
LSYN C* t td s TDA TA V A L ID t rd h t td s V A L ID t td h
F IL T E R SA MPLES DA TA
Figure 14. TDATA Setup/Hold Timing
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C L K IN
SYNC
LSYN C * t df DRDY t ec ERROR *N o te : F o r o v e rw rite c a s e , D R D Y w ill re m a in h ig h . t dr
Figure 15. DRDY Timing
C LK IN t rh
t rs
RESET
t ss
SYNC
t sh
Figure 16. RESET Timing
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CS5322 SWITCHING CHARACTERISTICS (continued)
Parameter MCLK Frequency MCLK Duty Cycle Rise Times: Fall Times: Any Digital Input Any Digital Output Any Digital Input Any Digital Output (Note 25) (Note 25) trise tfall tss tsh tmss tmsh (Note 26) tmsd (Note 24) Symbol fc Min 0.512 40 20 20 Typ 1.024 50 50 30 50 90 Max 1.1 60 100 200 100 200 Units MHz % ns ns ns ns ns ns ns ns ns
SYNC Setup Time to CLKIN rising SYNC Hold Time after CLKIN rising CLKIN edge to MCLK edge MCLK rising to Valid MDATA MSYNC Delay from MCLK rising
Notes: 24. If MCLK is removed, the modulator will enter the power down mode. 25. Excludes MCLK input. MCLK should be driven with a signal having rise and fall times of 25 ns or faster. 26. Only the rising edge of MSYNC relative to MCLK is used to synchronize the device. MSYNC can return low at any time as long as it remains high for at least one MCLK cycle.
C L K IN
t ss
t sh
SYNC
LSYN C* t m ss
M C LK
t m sd MSYNC t m sh M DATA F IL T E R SA M PLES DATA
t m sd
t m sh V A L ID D A T A V A L ID D A T A
M FLG
* In te rn a l tim in g s ig n a l g e n e ra te d in th e C S 5 3 2 2
Figure 17. CS5321/CS5322 Interface Timing
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CS5322 DIGITAL CHARACTERISTICS (TA = (See Note 1); VD+ = 5.0 V 5%; GND = 0 V;
measurements performed under static conditions) Parameter High-Level Input Drive Voltage Low-Level Input Drive Voltage High-Level Input Threshold Low-Level Input Threshold High-Level Output Voltage IOUT = -40A Low-Level Output Voltage IOUT = +1.6 mA Input Leakage Current Digital Input Capacitance Digital Output Capacitance Three-State Leakage Current (Note 27) (Note 27) (Note 28) (Note 28) VOH VOL ILKG IOZ CIN COUT Symbol VIH VIL Min (VD+)-0.3 (VD+)-1.0 (VD+)-0.6 Typ 9 9 Max 0.3 1.0 0.4 10 10 Units V V V V V V A A pF pF
All pins except MFLG, SOD
Notes: 27. Device is intended to be driven with CMOS logic levels. 28. Device is intended to be interfaced to CMOS logic. Resistive loads are not recommended on these pins.
CS5322 RECOMMENDED OPERATION CONDITIONS (Voltages with respect to GND =
0 V) Parameter DC Supply: Positive Negative Ambient Operating Temperature -BL (Note 29) VD+ VDTA 4.75 -4.75 -40 5.0 -5.0 5.25 -5.25 +85 V V C Symbol Min Typ Max Units
Notes: 29. The maximum voltage differential between the Positive Supply of the CS5321 and the Positive Digital Supply of the CS5322 must be less than 0.25 V.
CS5322 ABSOLUTE MAXIMUM RATINGS * (Voltages with respect to GND = 0 V)
Parameter DC Supply: Positive Negative Input Current, Any Pin Except Supplies Digital Input Voltage Storage Temperature (Note 30) (Note 29) VD+ VDIin VIND Tstg -0.3 0.3 -0.3 -65 (VD+)+0.3 -6.0 10 (VD+)+0.3 150 V V mA V C Symbol Min Typ Max Units
Notes: 30. Transient currents of up to 100 mA will not cause SCR latch up. *WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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2. GENERAL DESCRIPTION
The CS5321 is a fourth-order CMOS monolithic analog modulator designed specifically for very high resolution measurement of signals between dc and 1600 Hz. Configuring the CS5321 with the CS5322 FIR filter results in a high resolution A/D converter system that performs sampling and A/D conversion with a dynamic range exceeding 120 dB. The CS5321 uses a fourth-order oversampling architecture to achieve high resolution A/D conversion. The modulator consists of a 1-bit A/D converter embedded in a negative feedback loop. The modulator provides an oversampled serial bit stream at 256 kbits per second (HBR=1) and 128 kbits per second (HBR=0) operating with a clock rate of 1.024 MHz. Figure 18 illustrates the CS5321 block diagram. The CS5322 is a monolithic digital Finite Impulse Response (FIR) filter with programmable decimation. The CS5322 and CS5321 are intended to be used together to form a unique high dynamic range ADC chipset. The CS5322 provides the digital anti-alias filter for the CS5321 modulator output. The CS5322 consists of: a multi-stage FIR filter, four registers (status, data, offset, and configuration), a flexible serial input and output port, and a 2-channel input data multiplexer that selects data from the CS5321 (MDATA) or user test data (TDATA). The CS5322 decimates (64x to 4096x) the output to any of seven selectable up-date periods: 16, 8, 4, 2, 1, 0.5 and 0.25 milliseconds. Data is output from the digital filter in a 24-bit serial format. Figure 19 illustrates the CS5322 Block Diagram.
Vdd1
Vss1
AGND
Vdd2
Vss2 Digital
DGND LPWR OFST MFLG
Osc. Detect AINR AIN+ AIN-
Control
Clock A/D Generation
HBR MCLK MSYNC MDATA
D/A VREF+ VREF-
MDATA
Figure 18. CS5321 Block Diagram
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S ID CSEL PW DN ORCAL USEOR DECC DECB DECA H /S SCLK C L K IN RESET SYNC CS R /W M FLG DRDY ERROR MSYNC M C LK
STATUS R EG
TDATA
M D ATA
C O N F IG R E G C O N F IG M U X
DATA M UX
F IR 1
F IR 2
CONTROL
F IR 3
DATA REG
B IT S E L E C T
B IT S E L E C T
RSEL
MUX
SOD
Figure 19. CS5322 Block Diagram
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2.1 Analog Input
The CS5321 modulator uses a switched capacitor architecture for its signal and voltage reference inputs. The signal input uses three pins; AINR, AIN+, and AIN-. The AIN- pin acts as the return pin for the AINR and AIN+ pins. The AINR pin is a switched capacitor "rough charge" input for the AIN+ pin. The input impedance for the rough charge pin (AINR) is 1/fC where f is two times the modulator sampling clock rate and C is the internal sampling capacitor (about 40 pF). Using a 1.024 MHz master clock (HBR = 1) yields an input impedance of about 1/(512 kHz)X(40 pF) or about 50 k. Internal to the chip the rough charge input precharges the sampling capacitor used on the AIN+ input, therefore the effective input impedance on the AIN+ pin is orders of magnitude above the impedance seen on the AINR pin. The analog input structure inside the VREF+ pin is very similar to the AINR pin but includes additional circuitry whose operating current can change over temperature and from device to device. Therefore, if gain accuracy is important, the VREF+ pin should be driven from a low source impedance. The current demand of the VREF+ pin will produce a voltage drop of approximately 45 mV across the 200 source resistor of Figure 20 and Figure 21 Option A with MCLK = 1.024 MHz, HBR = 1, and temperature = 25C. When the CS5321 modulator is operated with a 4.5 V reference it will accept a 9 V p-p input signal, but modulator loop stability can be adversely affected by high frequency out-of-band signals. Therefore, input signals must be band-limited by an input filter. The -3 dB corner of the input filter must be equal to the modulator sampling clock divided by 64. The modulator sampling clock is MCLK/4 when HBR = 1 or MCLK/8 when HBR = 0. With MCLK = 1.024 MHz, HBR = 1, the modulator sampling clock is 256 kHz which requires an input filter with a -3 dB corner of 4 kHz. The bandlimiting may be accomplished in an amplifier stage ahead of the CS5321 modulator or with the RC input filter at the AIN+ and AINR input pins. The RC filter at the AIN+ and AINR pins is recommended to reduce the "charge kick" that the driving amplifier sees as the switched capacitor sampling is performed. Figure 20 illustrates the CS5321 and CS5322 system connections. The input components on AINR and AIN+ should be identical values for optimum performance. In choosing the components the capacitor should be a minimum of 0.1 F (C0G dielectric ceramic preferred). For minimum board space, the RC components on the AINR input can be removed, but this will force the driving amplifier to source the full dynamic charging current of the AINR input. This can increase distortion in the driving amplifier and reduce system performance. In choosing the RC filter components, increasing C and minimizing R is preferred. Increasing C reduces the instantaneous voltage change on the pin, but may require paralleling capacitors to maintain smaller size (the recommended 0.1 F C0G ceramic capacitor is larger than other similar-valued capacitors with different dielectrics). Larger resistor values will increase the voltage drop across the resistor as the recharging current charges the switched capacitor input.
2.2 The OFST Pin
The CS5321 modulator can produce "idle tones" which occur in the passband when the input signal is steady state dc signal within about 50 mV of bipolar zero. In the CS5321 these tones are about 135 dB down from full scale. The user can force these idle tones "out-of-band" by adding 100 mV of dc offset to the signal at the AIN input. Alternately, if the user circuitry has a low offset voltage such that the input signal is within 50 mV of bipolar zero when no AC signal is present, the OFST pin on the CS5321 can be activated. When OFST = 1, +100 mV of input referred offset will be
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added internal to the CS5321 and guarantee that any idle tones present will lie out-of-band. The user should be certain that when OFST is active (OFST =1) that the offset voltage generated by the user circuitry does not negate the offset added by the OFST pin. See the Voltage Reference section of this data sheet for voltage reference requirements. The modulator is a fourth order delta-sigma and is therefore conditionally stable. The modulator may go into an oscillatory condition if the analog input is overranged. Input signals which exceed either plus or minus full scale by more than 5 % can introduce instability in the modulator. If an unstable condition is detected, the modulator will be reduced to a first order system until loop stability is achieved. If this occurs the MFLG pin will transition from a low to a high and result in an error bit being set in the CS5322. The input signal must be reduced to within the full scale range of the converter for at least 32 MCLK cycles for the modulator to recover from this error condition.
2.3 Input Range and Overrange Conditions
The analog input is applied to the AIN+ and AINR pins with the AIN- pin connected to GND. The input is fully differential but for proper operation the AIN- pin must remain at GND potential. The analog input span is defined by the voltage applied between the VREF+ and VREF- input pins.
+5V Analog Supply
10 F
+ 0.1 F 2 1 22
0.1 F
+5 V Digital Supply
21 VD+
0.01 F 20
Vdd1 GND1
Vdd2
23 GND11 28 27 26 25 MSYNC MFLG MCLK 24 20 Control
DGND 25 SID 24 SOD SCLK 26 1 28 Serial Data Interface 27 RSEL ERROR 12 CSEL 23
OFST LPWR +4.5V VREF
200 0.1 F
5 + 68 F TANT. 6 VREFVREF+
HBR
Logic 5 6 7 10 MDATA
CS MSYNC MFLG MCLK R/W 22 DRDY
402
10 0.1 F COG 9 0.1 F COG AIN+ 8 AIN14 13 12 11 7 4 0.1 F AINR
18 MDATA
Signal Source
402
CS5321
17 MDATA 11
CS5322
H/S Test Data TDATA PWDN USEOR ORCAL GND8 GND9 19 GND10 15 16 Clock Source 2 SYNC 3 CLKIN DECA DECB DECC RESET VD+ +5 V Digital Supply 8
0.01 F
13 14 15 19 18 17 16 4 Hardware Control
GND7
GND6 GND5 GND4 GND3
GND2 Vss1
3
V ss2
21
0.1 F
DGND 9 Unused logic inputs must be connected to DGND or VD+
-5V Analog Supply
10 F
+
Figure 20. System Connection Diagram
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2.4 Voltage Reference
The CS5321 is designed to operate with a voltage reference in the range of 4.0 to 4.5 Volts. The voltage reference is applied to the VREF+ pin with the VREF- pin connected to the GND. A 4.5 V reference will result in the best S/N performance but most 4.5 V references require a power supply voltage greater than 5.0 V for operation. A 4.0 V reference can be used for those applications which must operate from only 5.0 V supplies, but will yield a S/N slightly lower (1-2 dB) than when using a 4.5 V reference. The voltage reference should be designed to yield less than 2 Vrms of noise in band at the VREF+ pin of the CS5321. The CS5322 filter selection will determine the bandwidth over which the voltage reference noise will affect the CS5321/22 dynamic range. For a 4.5 V reference, the LT1019-4.5 voltage reference yields low enough noise if the output is filtered with a low pass RC filter as shown in Figure 21 Option A. The filter in Figure 21 Option A is acceptable for most spectral measurement applications, but a buffered version with lower source impedance (Figure 21 Option B) may be preferred
10 0.1 F
for dc-measurement applications. Due to its dynamic (switched-capacitor) input the input impedance of the +VREF pin of the CS5321 will change any time MCLK or HBR is changed. Therefore the current required from the voltage reference will change any time MCLK or HBR is changed. This can affect gain accuracy due to the high source impedance of the filter resistor in Figure 20 and Figure 21 Option A. If gain error is to be minimized, especially when MCLK or HBR is changed, the voltage reference should have lower output impedance. The buffer of Figure 21 Option B offers lower output impedance and will exhibit better system gain stability.
2.5 Clock Source
For proper operation, the CS5321 must be provided with a CMOS-compatible clock on the MCLK pin. The MCLK for the CS5321 is usually provided by the CS5322 filter. MCLK is usually 1.024 MHz to set the seven selectable output word rates from the CS5322. The MCLK frequency can be as low as 250 kHz and as high as 1.2 MHz. The choice of clock frequency can affect performance; see the Performance section of the data sheet. The clock
+ 9 to 15V
Option A
200 0.1 F + 68 F To VRE F+
L T 1 0 1 9 -4 .5
Option B
+ 9 to 1 5 V
1k 10k
+
4 9 .9 + 100 F AL 100 F AL
-
100 0.1 F 1k
+
+
68 F T ant
To VRE F+
LT 1007
Figure 21. 4.5 Voltage Reference with two filter options
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must have less than 300 ps jitter to maintain data sheet performance from the device. The CS5321 is equipped with loss of clock detection circuitry which will cause the CS5321 to enter a powereddown state if the MCLK is removed or reduced to a very low frequency. The HBR pin on the CS5321 modifies the sampling clock rate of the modulator. When HBR = 1, the modulator sampling clock will be at MCLK/4; with HBR = 0 the modulator sampling clock will be at MCLK/8. The chip set will exhibit about 3 dB less S/N performance when the HBR pin is changed from a logic "1" to a logic "0" for the same output word rate from the CS5322. CS5321 must be furnished with an MSYNC signal prior to data conversion. The MSYNC signal, generated by the CS5322, resets the MCLK counter-divider in the CS5321 to the correct phase so that the bitstream can be properly sampled by the CS5322 digital filter. When operated with the CS5322 digital filter the output codes from the CS5321/22 will range from approximately decimal -5,242,880 to +5,242,879 for an input to the CS5321 of 4.5 V. Table 1 illustrates the output coding for various input signal amplitudes. Note that with a signal input defined as a full scale signal (4.5 V with VREF+ = 4.5 V) the CS5321/22 chipset does not output a full scale digital code of 8,388,607 but is scaled to a lower value to allow some overrange capability. Input signals can exceed the defined full scale by up to 5% and still be converted properly.
CS5322 Filter Output Code HEX 53FFFF(H) 4FFFFF(H) 000000(H) B00000(H) AC0000(H) Decimal +5505023 +5242879 0 -5242880 -5505024 Error Flag Possible
2.6 Low Power Mode
The CS5321 includes a low power operating mode (LPWR =1). When operated with LPWR = 1, the CS5321 modulator sampling clock must be restricted to rates of 128 kHz or less. Operating in low power mode with modulator sample rates greater than 128 kHz will greatly degrade performance.
2.7 Digital Interface and Data Format
The MCLK signal (normally 1.024 MHz) is divided by four, or by eight inside the CS5321 to generate the modulator oversampling clock. The HBR pin determines whether the clock divider inside the CS5321 divides by four (HBR =1) or by eight (HBR = 0). The modulator outputs a ones density bit stream from its MDATA and MDATA pins proportional to the analog input signal, but at a bit rate determined by the modulator over sampling clock. For proper synchronization of the bitstream, the
Modulator Input Signal > (+VREF + 5%) (+VREF + 5%) +VREF 0V -VREF - (+VREF +5%) > - (+VREF +5%)
Error Flag Possible
Table 1. Output Coding for the CS5321 and CS5322 Combination
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2.8 Performance
Figure 22, 23 and 24 illustrate the spectral performance of the CS5321/22 and chipset when operating from a 1.024 MHz master clock. Ten 1024 point FFTs were averaged to produce the plots. Figure 22 illustrates the chip set with a 100 Hz, -20 dB input signal. The sample rate was set at 1 kHz. Dynamic range is 122 dB. The dynamic range calculated by the test soft-ware is reduced somewhat in Figures 23 and 24 because of jitter in the signal test oscillator. Jitter in the 100 Hz signal source is interpreted by the signal processing software to be increased noise. The choice of master clock frequency will affect performance. The CS5321 will exhibit the best Signal to Distortion performance with slower modulator sampling clock rates as slower sample rates allow more time for amplifier settling. For lowest offset drift, the CS5321 should be operated with MCLK = 1.024 MHz and HBR = 1. Slower modulator sampling clock rates will exhibit more offset drift. Changing MCLK to 512 kHz (HBR = 1) or changing HBR to zero (MCLK = 1.024 MHz) will cause the drift rate to double. Offset drift is not linear over temperature so it is difficult to specify an exact drift rate. Offset drift characteristics vary from part to part and will vary as the power supply voltages vary. Therefore, if the CS5321 is to be used in precision dc measurement applications where offset drift is to be minimized, the power supplies should be well regulated. The CS5321 will exhibit about 6 ppm/C of offset drift with MCLK = 1 and HBR = 1. Gain drift of the CS5321 itself is about 5 ppm/C and is not affected by either modulator sample rate or by power supply variation.
0 -20 -40 -60 -80 -100 -120 -140 -160 -180 0 500
Figure 22. 1024 Point FFT Plot with -20 dB Input, 100 Hz Input, ten averages
D yn a m ic R a n g e = 1 2 2 .0 d B HBR = 1 OFST = 0 LPW R = 0
0 -20 -40 -60 -80 -100 -120 -140 -160 -180 0 500
see text
S /D = 1 1 6 .0 d B S /N = 1 1 8 .4 d B S /N + D = 1 1 4 .2 d B HBR = 1 OFST = 0 LPW R = 0
Figure 23. 1024 Point FFT Plot with Full Scale Input, 100 Hz Input, HBR = 1, ten averages
0 -20 -40 -60 -80 -100 -120 -140 -160 -180 0 500
see text
S /D = 1 2 2 .7 d B S /N = 1 1 7 .1 d B S /N + D = 1 1 6 .4 d B HBR = 0 OFST = 0 LPW R = 0
Figure 24. 1024 Point FFT Plot with Full Scale Input, 100 Hz Input, HBR = 0, ten averages
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2.9 Power Supply Considerations
The system connection diagram, Figure 20, illustrates the recommended power supply arrangements. There are two positive power supply pins for the CS5321 and two negative power supply pins. Power must be supplied to all four pins and each of the supply pins should be de-coupled with a 0.1 F capacitor to the nearest ground pin on the device. When used with the CS5322 digital filter, the maximum voltage differential between the positive supplies of the CS5321 and the positive digital supply of the CS5322 must be less than 0.25 V. Operation beyond this constraint may result in loss of analog performance in the CS5321/22 system performance. Many seismic or portable data acquisition systems are battery powered and utilize dc-dc converters to generate the necessary supply voltages for the system. To minimize the effects of power supply interference, it is desirable to operate the dc-dc converter at a frequency which is rejected by the digital filter, or locked to the modulator sample clock rate. A synchronous dc-dc converter, whose operating frequency is derived from the 1.024 MHz clock used to drive the CS5322, will minimize the potential for "beat frequencies" appearing in the passband between dc and the corner frequency of the digital filter.
2.11 RESET Operation
The RESET pin puts the CS5322 into a known initialized state. RESET is recognized on the next CLKIN rising edge after the RESET pin has been brought high (RESET=1). All internal logic is initialized when RESET is active. Normal device operation begins on the second CLKIN rising edge after RESET is brought low. The CS5322 will remain in an idle state, not performing convolutions, until triggered by a SYNC event. A RESET operation clears memory, sets the data output register, offset register, and status flags to all zeroes, and sets the configuration register to the state of the corresponding hardware pins (PWDN, ORCAL, DECC, DECB, DECA, USEOR, and CSEL). The reset state is entered on power on, independent of the RESET pin. If RESET is low, the first CLKIN will exit the power on reset state.
2.12 Power-down Operation
The PWDN pin puts the CS5322 into the powerdown state. The power-down state is entered on the first CLKIN rising edge after the PWDN pin is brought high. While in the power-down state, the MCLK and MSYNC signals to the CS5321 analog modulator are held low. The loss of the MCLK signal to the modulator causes it to power-down. The signals on the MDATA and MFLG pins are ignored. The serial interface of the CS5322 remains active allowing read and write operations. Information in the data register, offset register, configuration register, and convolution data memory are maintained during power-down. The internal controller requires 64 clock cycles after PWDN is asserted before CLKIN stops. The CS5322 exits the power-down state on the first CLKIN rising edge after the PWDN pin is brought low. The CS5322 then enters an idle state until triggered by a SYNC event.
2.10 Power Supply Rejection Ratio
The PSRR of the CS5321 is frequency dependent. The CS5322 digital filter attenuation will aid in rejection of power supply noise for frequencies above the corner frequency setting of the CS5322. For frequencies between dc and the corner frequency of the digital filter, the PSRR is nearly constant at about 60 dB.
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To avoid possible high current states while in the power down state, the following conditions apply: 1) CLKIN must be active for at least 64 clock cycles after PWDN entry. 2) CSEL and TDATA must not both be asserted high. SCLK falling edge, each SCLK rising edge shifts out a new bit. Status reads are 16 bits, and data reads are 24 bits. Both streams are supplied as MSB first, LSB last. In the event more SCLK pulses are supplied than necessary to clock out the requested information, trailing zeroes will be output for data reads and trailing LSB's for status reads. If the read operation is terminated before all the bits are read, the internal bit pointer is reset to the MSB so that a re-read will give the same data as the first read, with one exception. The status error flags are cleared on read and will not be available on a re-read. The status error flags must be read before entering the power-down state. If an error has occurred before entering powerdown and the status bit (ERROR) has not been read, the status bits (ERROR, OVERWRITE, MFLG, ACC1 and ACC2) may not be cleared on status reads. Upon exiting the powerdown state and entering normal operation, the user may be flagged that an error is still present. The SOD pin floats when read operation is deactivated (R/W=1, CS=1). This enables the SID and SOD pins to be tied together to form a bi-directional serial data bus. There is an internal nominal 100 k pull-up resistor on the SOD pin.
2.13 SYNC Operation
The SYNC pin is used to start convolutions and synchronize the CS5322 and CS5321 to an external sampling source or timing reference. The SYNC event is recognized on the first CLKIN rising edge after the SYNC pin goes high. SYNC may remain high indefinitely. Only the sequence of SYNC rising followed by CLKIN rising generates a SYNC event. The SYNC event aligns the output sample and causes the filter to begin convolutions. The first SYNC event causes an immediate DRDY provided DRDY is low. Subsequent data ready events will occur at a rate determined by the decimation rate inputs DECC, DECB, and DECA. Multiple SYNC events can be applied with no effect on operation if they are perfectly timed according to the decimation rate. Any SYNC event not in step with the decimation rate will cause a realignment and loss of data.
2.15 Serial Write Operation
Serial write is used to write data to the configuration register. The CS, R/W, SCLK and SID pins control the serial write operation. The serial write operation is activated when CS goes low (CS=0) with R/W pin low (R/W=0). Serial input data on the SID pin is sampled on the falling edge of SCLK. The input bits are stored in a temporary buffer until either the write operation is terminated or 8 bits have been received. The data is then parallel loaded into the configuration register. If fewer than 8 bits are input before the write termination, the other bits may be indeterminate.
2.14 Serial Read Operation
Serial read is used to obtain status or conversion data. The CS, R/W, SCLK, RSEL, and SOD pins control the read operation. The serial read operation is activated when CS goes low (CS=0) with the R/W pin high (R/W=1). The RSEL pin selects between conversion data (data register) or status information (status register). The selected serial bit stream is output on the SOD (Serial Output Data) pin. On read select, SCLK can either be high or low, the first bit appears on the SOD pin and should be latched on the falling edge of SCLK. After the first
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Note that a write will occur when CS = 0 and R/W = 0 even if SCLK is not toggled. Failure to clock in data with the appropriate number of SCLKs can leave the configuration register in an indeterminate condition. The serial bit stream is received MSB first, LSB last. The order of the input control data is PWDN first, followed by ORCAL, USEOR, CSEL, Reserved, DECC, DECB, and DECA. The configuration data bits are defined in Table 2. The configuration data controls device operation only when in the software mode, i.e., the H/S pin is low (H/S = 0). The Reserved configuration data bit must always be written low. cept when ORCAL = 1 and the CS5322 is RESET as this toggles the ORCAL internally). After ORCAL has been toggled, the SYNC signal must be applied to the CS5322. The filter settles on the input value in 56 output words. The output word rate is determined by the state of the decimation rate control pins, DECC, DECB, and DECA. On the 57th output word, the CS5322 issues the ORCALD status flag, outputs the offset data sample, and internally loads the offset register. During calibration, the offset register value is not used. If USEOR is high (USEOR=1), subsequent samples will have the offset subtracted from the output. The state of USEOR must remain high for the complete duration of the convolution cycle. If USEOR is low (USEOR=0), the output word is not corrected, but the offset register retains its value for later use. The results of the last calibration will be held in the offset register until the end of a new calibration, or until the CS5322 is reset using the RESET pin. USEOR does not alter the offset register value, only its usage. To restart a calibration, ORCAL and SYNC must be taken low for at least one CLKIN cycle. ORCAL must then be taken high. The calibration will restart on the next SYNC event. If the ORCAL pin remains in a high state, only a single calibration will start on the first SYNC signal.
2.16 Offset Calibration Operation
The offset calibration routine computes the offset produced by the CS5321 modulator and stores this value in the offset register. The USEOR pin or bit determines if the offset register data is to be used to correct output words. After power is applied to the chip set the CS5322 must be RESET. To begin an offset calibration, the CS5321 analog input must represent the offset value. Then in software mode (H/S = 0) the ORCAL bit must be toggled from a low to a high. In hardware mode the ORCAL pin must be toggled low for at least one CLKIN cycle, then taken high (ex-
Input Bit # 1 (MSB) 2 3 4 5 6 7 8 (LSB)
Equivalent Hardware Function PWDN ORCAL USEOR CSEL Reserved DECC DECB DECA
Description Standby mode Self-offset calibration Use Offset Register Channel Select Factory use only Filter BW selection Filter BW selection Filter BW selection
Table 2. Configuration Data Bits
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2.17 Status Bits
The Status Register is a 16-bit register which allows the user to read the flags and configuration settings of the CS5322. Table 3 documents the data bits of the Status Register. The ERROR bit and ERROR pin value are the OR'ed result of OVERWRITE, MFLG, ACC1, and ACC2. The ERROR bit is active high whenever any of the four error bits are set due to a fault condition. The ERROR pin output is active low and has a nominal 100 k internal pull-up resistor. The OVERWRITE bit is set when new conversion data is ready to be loaded into the data register, but the previous data was not completely read out. This can occur on either of two conditions: a read operation is in progress or a read operation was started, then aborted, and not completed. These two conditions are data read attempts. The attempt is identified by the first SCLK low edge (MSB read) of a data register read. If a data register read is not attempted, the CS5322 assumes that data is not wanted and does not assert OVERWRITE, and the old data is over-written by the new data. On an OVERWRITE condition, the old partially read data is preserved, and the new data word is lost. Status reads have no effect on OVERWRITE assert operations. The OVERWRITE bit is cleared on a status register read or RESET. The MFLG error bit reflects the CS5321 MFLG signal. Any high level on the CS5322 MFLG pin will set the MFLG status bit. The bit is cleared on a status register read or RESET operation, only if the MFLG pin on the CS5322 has returned low. A internal nominal 100 k pulldown resistor is on the MFLG pin. The accumulator error bits, ACC1 and ACC2, indicate that an underflow or overflow has occurred in the FIR1 filter for ACC1, or the FIR2 and FIR3 filters for ACC2. Both errors are cleared on a status read, provided the error conditions are no longer
Output Bit # 1 (MSB) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Function Error OVERWRITE Error MFLG Error ACC1 Error ACC2 Error DRDY 1SYNC ORCALD PWDN ORCAL USEOR CSEL Reserved DECC DECB DECA
Description Detects one of the errors below Overwrite Error Modulator Flag Error Accumulator 1 Error Accumulator Error Data Ready First sample after SYNC Offset calibration done Standby mode Self-offset Calibration Use Offset Register Channel Select Factory use only Bandwidth Selection Status Bandwidth Selection Status Bandwidth Selection Status
Table 3. Status Data (from the SOD Pin)
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present. In normal operation the ACC1 error will only occur when the input data stream to FIR1 is all 1's for more than 32 bits. The ACC2 error cannot occur in normal operation. The DRDY bit reflects the state of the DRDY pin. DRDY rising edge indicates that a new data word has been loaded into the data register and is available for reading. DRDY will fall after the SCLK falling edge that reads the data register LSB. If nodata read attempt is made, DRDY will pulse low for 1/2 CLKIN cycle, providing a positive edge on the new data availability. In the OVERWRITE case, DRDY remains high because new data is not loaded at the normal end of conversion time. The 1SYNC status bit provides an indication of the filter group delay. It goes high on the second output sample after SYNC and is valid for only that sample. For repetitive SYNC operations, SYNC must run at one fourth the output word rate or slower to avoid interfering with the 1SYNC operation. With these slower repetitive SYNC's or non-periodic SYNC's separated by at least three output words, 1SYNC will occur on the second output sample after SYNC. ORCALD indicates that calibration of the offset register is complete and the offset sample is available in the output register. This flag is high only during that sample and is otherwise low. The remaining five status bits (PWDN, ORCAL, USEOR, CSEL, Reserved, DECC, DECB, and DECA) provide configuration readback for the user. These bits echo the control source for the CS5322 such that in the hardware mode (H/S=1), they follow the corresponding input pins. In host mode (H/S=0) they follow the corresponding configuration bits. A brief explanation of the eight bits are as follows: PWDN - When high, indicates that the CS5322 is in the power-down state. ORCAL - When high, indicates a potential calibration start. USEOR - When high, indicates the Offset Register is used. During calibration, this bit will read zero indicating the offset register is not being used during calibration. CSEL- When high, TDATA is selected as the filter source. When low, the MDATA output signal from the CS5321 is selected as the input source to the filter. Reserved - Always read low. DECC, DECB, and DECA - Indicate the decimation rate of the filter and are defined in Table 4.
DECC 0 0 0 0 1 1 1 1
DECB 0 0 1 1 0 0 1 1
DECA 0 1 0 1 0 1 0 1
Output Word Rate (Hz) 62.5 125 250 500 1000 2000 4000 Reserved
Clocks Filter Output 16384 8192 4096 2048 1024 512 256 -
Table 4. Bandwidth Selection: Truth Table
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2.18 Board Layout Considerations
All of the 0.1 F filter capacitors on the power supplies, AIN+, and AINR, should be placed very close to the chip and connect to the nearest ground pin on the device. The capacitors between VREF+ and VREF- should be located as close to the chip as possible. The 0.l F capacitors on the AIN+ and AINR pins should be placed with their leads on the same axis, not side-by-side. If these capacitors are placed side-by-side their electric fields can interact and cause increased distortion. The chip should be surrounded with a ground plane. Trace fill should be used around the analog input components.
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3. CS5321 PIN DESCRIPTIONS
Power Supplies Vdd1 - Positive Power One, PIN 2 Positive supply voltage. Nominally +5 Volts. Vdd2 - Positive Power Two, PIN 22 Positive supply voltage. Nominally +5 Volts. Vss1 - Negative Power One, PIN 3 Negative supply voltage. Nominally -5 Volts. Vss2 - Negative Power Two, PIN 21 Negative supply voltage. Nominally -5 Volts. GND1 through GND11 - Ground, PINS 1, 4, 7, 11, 12, 13, 14, 15, 16, 19, 23. Ground reference. Analog Inputs AIN+ - Positive Analog Input, PIN 9 Nominally 4.5V AIN- - Negative Analog Input, PIN 8 This pin is tied to ground.
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AINR - Analog Input Rough, PIN 10 Allows a non-linear current to bypass the main external anti-aliasing filter which if allowed to happen, would cause harmonic distortion in the modulator. Please refer to the System Connection Diagram and the Analog Input and Voltage Reference section of the data sheet for recommended use of this pin. VREF+ - Positive Voltage Reference Input, PIN 5 This pin accepts an external +4.5 V voltage reference. VREF- - Negative Voltage Reference Input, PIN 6 This pin is tied to ground. Digital Inputs MCLK - Clock Input, PIN 20 A CMOS-compatible clock input to this pin (nominally 1.024 MHz) provides the necessary clock for operation of the modulator and data output portions of the A/D converter. MCLK is normally supplied by the CS5322 MSYNC - Modulator Sync, PIN 25 A transition from a low to high level on this input will re-initialize the CS5321. MSYNC resets a divider-counter to align the MDATA output bit stream from the CS5321 with the timing inside the CS5322. OFST - Offset, PIN 28 When high, adds approximately 100 mV of input referred offset to guarantee that any zero input limit cycles are out of band if present. When low, zero offset is added. LPWR - Low Power Mode, PIN 27 The CS5321 power dissipation can be reduced from its nominal value of 55 mW to 30 mW under the following conditions: LPWR=1; MCLK = 512 kHz, HBR=1; or LPWR=1; MCLK = 1.024 MHz, HBR=0 HBR - High Bit Rate, Pin 26 Selects either 1 4 MCLK (HBR=1) or 1 8MCLK (HBR=0) for the modulator sampling clock. Digital Outputs MDATA - Modulator Data Output, PIN 18 Data will be presented in a one-bit serial data stream at a bit rate of 256 kHz (HBR=1) or 128 kHz (HBR=0) with MCLK operating at 1.024 MHz. MDATA - Modulator Data Output, PIN 17 Inverse of the MDATA output. MFLG - Modulator Flag, PIN 24 A transition from a low to high level signals that the CS5321 modulator is unstable due to an overrange on the analog input
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4. CS5322 PIN DESCRIPTIONS
CHIP SELECT FRAME SYNC CS SYNC R/W RSEL SCLK SID
5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 27 2 6 25 24 23 22 21 20 19
READ/WRITE REGISTER SELECT SERIAL CLOCK SERIAL INPUT DATA SERIAL OUTPUT DATA DATA READY POSITIVE DIGITAL POWER DIGITAL GROUND DECIMATION RATE CONTROL DECIMATION RATE CONTROL DECIMATION RATE CONTROL
CLOCK INPUT CLKIN RESET RESET MODULATOR SYNC MSYNC MODULATOR FLAG MODULATOR CLOCK POSITIVE DIGITAL POWER DIGITAL GROUND MFLG MCLK VD+ DGND CS5322
TOP VIEW
SOD DRDY VD+ DGND DECA DECB DECC
ERROR ERROR FLAG
MODULATOR DATA MDATA TEST DATA TDATA CHANNEL SELECT HARDWARE/SOFTWARE MODE CSEL H/S
ORCAL OFFSET CALIBRATION
POWER DOWN PWDN
USEOR USE OFFSET REGISTER
Power Supplies VD+ - Positive Digital Power, Pin 8, 21 Positive digital supply voltage. Nominally +5 volts. DGND - Digital Ground, Pin 9, 20 Digital ground reference. Digital Outputs MCLK - Modulator Clock Output, Pin 7 A CMOS-compatible clock output (nominally 1.024 MHz) that provides the necessary clock for operation of the modulator. MSYNC - Modulator Sync, Pin 5 The transition from a low to high level on this output will re-initialize the CS5321. ERROR - Error Flag, Pin 23 This signal is the output of an open pull-up NOR gate with a nominal 100 k pull-up resistor to which the error status data (OVERWRITE error, MFLG error, ACC1 error and ACC2 error) are inputs. When low, it notifies the host processor that an error condition exists. The ERROR signal can be wire OR'd together with other filters' outputs. The value of the internal pull-up resistor is 100 k. DRDY - Data Ready, Pin 22 When high, data is ready to be shifted out of the serial port data register.
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SOD - Serial Output Data, Pin 24 The output coding is 2's complement with the data bits presented MSB first, LSB last. Data changes on the rising edge of SCLK. An internal nominal 100 k pull-up resistor is included. Digital Inputs MDATA - Modulator Data, Pin 10 Data will be presented in a one-bit serial data stream at a bit rate of 256 kHz; (CLKIN = 1.024 MHz). TDATA - Test Data, Pin 11 Input for user test data. MFLG - Modulator Flag, Pin 6 A transition from a low to high level signals that the CS5321 modulator is unstable due to an over-range on the analog input. A Status Bit will be set in the digital filter indicating an error condition. An internal nominal 100 k pull-down resistor included on the input pin. RESET - Filter Reset, Pin 4 Performs a hard reset on the chip, all registers and accumulators are cleared. All signals to the device are locked out except CLKIN. The error flags in the Status Register are set to zero and the Data Register and Offset Register are set to zero. The configuration register is set to the values of the corresponding input pins. SYNC must be applied to resume convolutions after RESET deasserts. CLKIN - Clock Input, Pin 3 A CMOS-Compatible clock input to this pin (nominally 1.024 MHz) provides the necessary clock for operation the modulator and filter. SYNC - Frame Sync, Pin 2 Conversion synchronization input. This signal synchronizes the start of the filter convolution. More than one SYNC signal can occur with no effect on filter performance, providing the SYNC signals are perfectly timed at intervals equal to the output sample period. CSEL - Channel Select, Pin 12 When high, information on the TDATA pin is presented to the digital filter. A low causes data on the MDATA input to be presented to the digital filter. PWDN - Powerdown, Pin 14 Powers down the filter when taken high. Convolution cycles in the digital filter and the MCLK signal are stopped. The registers maintain their data and the serial port remains active. SYNC must be applied to resume convolutions after PWDN deasserts. DECA - Decimation Rate Control, Pin 18 See Table 4. DECB - Decimation Rate Control, Pin 17 See Table 4.
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DECC - Decimation Rate Control, Pin 16 See Table 4. H/S - Hardware/Software Mode Select, Pin 13 When high, the device pins control device operation; when low, the value entered by a prior configuration write controls device operation. CS - Chip Select, Pin 1 When high, all signal activity on the SID, R/W and SCLK pins is ignored. The DRDY and ERROR signals indicate the status of the chip's internal operation. R/W - Read/Write, Pin 28 Used in conjunction with CS such that when both signals are low, the filter inputs data from the SID pin on the falling edge of SCLK. If CS is low and R/W is high, the filter outputs data on the SOD pin on the rising edge of SCLK. R/W low floats the SOD pin allowing SID and SOD to be tied together, forming a bidirectional serial data bus. SCLK - Serial Clock, Pin 26 Clock signal generated by host processor to either input data on the SID input pin, or output data on the SOD output pin. For write, data must be valid on the SID pin on the falling edge of SCLK. Data changes on the SOD pin on the rising edge of SCLK. SID - Serial Data Input, Pin 25 Data bits are presented MSB first, LSB last. Data is latched on the falling edge of SCLK. RSEL - Register Select, Pin 27 Selects conversion data when high, or status data when low. USEOR - Use Offset Register, Pin 15 Use offset register value to correct output words when high. Output words will not be offset corrected when low. ORCAL - Offset Register Calibrate, Pin 19 Initiates an offset calibration cycle when SYNC goes high after ORCAL has been toggled from low to high. The offset value is output on the 57th word following SYNC. Subsequent words will have their offset correction controlled by USEOR.
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5. PARAMETER DEFINITIONS
Dynamic Range The ratio of the full-scale (rms) signal to the broadband (rms) noise signal. Broadband noise is measured with the input grounded within the bandwidth of 1 Hz to f3 Hz (See "CS5322 FILTER CHARACTERISTICS" on page 8). Units in dB. Signal-to-Distortion The ratio of the full-scale (rms) signal to the rms sum of all harmonics up to f3 Hz. Units in dB. Intermodulation Distortion The ratio of the rms sum of the two test frequencies (30 and 50 Hz) which are each 6 dB down from full-scale to the rms sum of all intermodulation components within the bandwidth of dc to f3 Hz. Units in dB. Full Scale Error The ratio of the difference between the value of the voltage reference and analog input voltage to the full scale span (two times the voltage reference value). This ratio is calculated after the effects of offset and the external bias components are removed and the analog input voltage is adjusted. Measurement of this parameter uses the circuitry illustrated in the System Connection Diagram. Units in %. Full Scale Drift The change in the Full Scale value with temperature. Units in %/C. Offset The difference between the analog ground and the analog voltage necessary to yield an output code from the CS5321/22 of 000000(H). Measurement of this parameter uses the circuit configuration illustrated in the System Connection Diagram. Units in mV. Offset Drift The change in the Offset value with temperature. Measurement of this parameter uses the circuit configuration illustrated in the System Connection Diagram. Units in V/C.
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6. PACKAGE DIMENSIONS
28L PLCC PACKAGE DRAWING
e D2/E2
E1 E
B
D1 D A
A1
INCHES DIM A A1 B D D1 D2 E E1 E2 e MIN 0.165 0.090 0.013 0.485 0.450 0.390 0.485 0.450 0.390 0.040 MAX 0.180 0.120 0.021 0.495 0.456 0.430 0.495 0.456 0.430 0.060 JEDEC #: MS-018
MILLIMETERS MIN MAX 4.043 4.572 2.205 3.048 0.319 0.533 11.883 12.573 11.025 11.582 9.555 10.922 11.883 12.573 11.025 11.582 9.555 10.922 0.980 1.524
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7. ORDERING INFORMATION
Model Temperature Package
CS5321-BL CS5321-BLZ (Lead Free) CS5322-BL CS5322-BLZ (Lead Free)
-55 to +85 C 28-pin PLCC -40 to +85 C
8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number Peak Reflow Temp 225 C 260 C 225 C 260 C 2 365 Days MSL Rating* Max Floor Life
CS5321-BL CS5321-BLZ (Lead Free) CS5322-BL CS5322-BLZ (Lead Free)
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
9. REVISION HISTORY
Revision PP3 F1 F2 F3 Date OCT 2003 AUG 2005 SEP 2005 NOV 2006
Initial Release. Update ordering information. MSL data added. Change CS5321 TA spec to -40 to +85 degrees. Change CS5321 TA spec to -55 to +85 degrees. Corrected Ordering Information from 28-SSOP to 28-PLCC.
Changes
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
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